The present invention relates to clock generation on integrated circuits (ICs). In particular, the invention relates to an apparatus that generates on-chip clock without external components, such as a crystal.
Clock generators play a critical role in modern integrated circuits. The stability of the clock is key to the performance of other systems on the IC that use the clock. For example, the signal-to-noise ratio (SNR) of an analog to digital converter (ADC), the stability of a UART communication port, and variation of power consumption at different temperatures and power supply voltages of a CPU are all subject to the stability of the clocks that drive them. Typically, a combination of a phase locked loop (PLL) and an off-chip crystal, which has high stability, is utilized to generate a highly stable clock for an IC. But the size of the crystal is often unacceptably big compared to ICs which are becoming smaller and smaller, in particular for applications that are limited by their PCB areas.
Fully on-chip clock generators are popular for ICs that emphasize small package size. Traditionally, the fully on-chip clock generator is a relaxation oscillator, which is made up of an on-chip resistor, a capacitor and active circuits such as comparators. However, the relaxation oscillator is often power hungry compared to PLL. For modern low power ICs, the relaxation oscillator often takes a large percentage of overall power consumption.
In a prior art relaxation oscillator 100, as shown in FIG. 1, a capacitor C1 must be charged and discharged at an output clock frequency Fclk. The two comparators 101 and 102 must make decisions in a time period much less than Tclk=1/Fclk to keep the temperature drift of Fclk low. Both make power consumption of the relaxation oscillator high.
Therefore, it would be desirable to provide a fully on-chip clock generator which does not require an external crystal and is power efficient.